• Sarang Kazeminia

  • Associate Professor
  • Electrical Engineering
Email:   
WebSite: https://faculty.uut.ac.ir/kazeminia

Short Bioghraphy

          
         
    

Research and Education Resume

[رزومه فارسی]

Journal Articles (19)

Conference Papers/Abstracts/Posters (25)
   
  • Name and Family
  • Sarang Kazeminia
  • Degree
  • Ph.D.
  • Academic Degree
  • Associate Professor
  • Department
  • Electrical Engineering
  • E-mail:
  • s.kazeminia@uut.ac.ir
 
 
 
         
     Research and Education Resume

Journal Articles (19)


1-Sarang Kazeminia, Arefeh Soltani, A low-jitter leakage-free digitally calibrated phase locked loop,Computers & Electrical Engineering, Elsevier, 2020, Volume 88, December 2020, 106865.

2-Sarang Kazeminia, Frequency-range enhanced delay locked loop based on varactor-loaded and current-controlled delay elements ,AEU - International Journal of Electronics and Communications, 2020, Volume 127, December 2020, 153477.

3-S Mahdavi, S Kazeminia, K Hadidi, A 17 MS/s SAR ADC with energy-efficient switching strategy,Analog Integr Circ Sig Process (Springer), 2020, 103, pages: 223–236.

4-Sarang Kazeminia، Sina Mahdavi, Offset Cancellation in a 800MS/s Single-Stage Comparator by Analog Trimming on the Body Voltage of PMOS Devices,TABRIZ JOURNAL OF ELECTRICAL ENGINEERING, 2019, Vol.49, No.2, Issue.88, pp:805-818.

5-Sarang Kazeminia، Amir Laal Shahsavar, Dual-path linearization technique for bandwidth enhancement in SAH circuits,AEU - International Journal of Electronics and Communications, 2019, Volume 110, October 2019, 152864.

6-Sarang Kazeminia، Sina Mahdavi, Highly-matched sub-ADC cells for pipeline analogue-to-digital converters,International Journal of Electronics, 2019, Volume 106, 2019 - Issue 12.

7-Sarang Kazeminia, A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs,Integration, The VLSI (Elsevier), 2019, Volume 65, March 2019, Pages 51-73.

8-Ali Ansari، Reza Abdi Behnagh، Dong Lin، Sarang Kazeminia, Modelling of Friction Stir Extrusion using Artificial Neural Network (ANN),International Journal of Advanced Design and Manufacturing Technology, 2018, Volume 11 , Number 4 Page(s) 1 To 12..

9-Sarang Kazeminia، Reza Abdi Behnagh، Milad Kalabkhani, Design and Manufacturing of a Low-Power Dual-Axis Sun Tracker Based on Novel Mechanical and Electrical Detectors,Modares Mechanical Engineering،Modares Mechanical Engineering, 2018, Volume 18, Issue 7 (11-2018).

10-Sarang Kazeminia، Roozbeh Abdollahi، Arash Hejazi, A fast-locking low-jitter digitally-enhanced DLL dynamically controlled for loop-gain and stability,Analog Integrated Circuits and Signal Processing، Springer, March 2018, 94, pages: 507–517.

11-Sarang Kazeminia، Khayrollah Hadidi, A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs,Integration، The VLSI Journal، Elsevier, 2018, Volume 61, March 2018, Pages 88-100.

12-Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei, A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs,Journal of Circuits Systems and Computers, 2015, Vol. 24, No. 07, 1550104 (2015).

13-Sarang Kazeminia, Obalit Shino, Ehsan Haghigh, Khayrollah Hadidi, Speed Enhancement and Kickback noise reduction in single-stage latched comparator improved for high-speed and low-noise analogue-to-digital converters,International Journal of Electronics Letters، Taylor & Francis, 2015, Volume 5, 2017 - Issue 1.

14-Sarang Kazeminia، Sobhan Sofi Mowloodi، Khayrollah Hadidi, A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge,Journal of Circuits System and Computers, 2015, Vol. 24, No. 01, 1550001 (2015).

15-Sarang Kazeminia, Abdollah Khoei, Khayrollah Hadidi, A Low-Jitter 20-110MHz DLL Based on a Simple PD and Common-Mode Voltage Level Corrected Differential Delay Elements,Journal of Information Systems & Telecommunication, 2014, Corpus ID: 110251343.

16-Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei، , Reanalyzing the basic bandgap reference voltage circuit considering thermal dependence of bandgap energy,Analog Integrated Circuits and Signal Processing، Springer, 29 December 2013, 79, pages141–147 (2014).

17-Sarang Kazeminia، Morteza Mousazadeh، Khayrollah Hadidi، Abdollah Khoei, A 500MS/s 600µW 300µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35µm 3.3v CMOS Process,IEICE Transactions on Electronics, 2011, 94-C (2011): 635-640..

18-Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei, A Novel Open Loop Structure for Phase Shifting and Frequency Synthesizing,IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2008, Volume E91-A Issue 2، Pages 491-496.

19-Sarang Kazeminia, Abdollah Khoei, Khayrollah Hadidi, High Speed High Precision Voltage-Mode MAX and MIN Circuits,Journal of Circuits، Systems and Computers, 2007, Vol. 16, No. 02, pp. 233-244 (2007).

Conference Papers/Abstracts/Posters (25)


1-Sarang Kazeminia, Maryam Ghafoorzadeh, Faeze Noruzpur, An extendable global clock high-speed binary counter compatible to the FPGA CLBs,24th International Conference on Mixed Design of Integrated Circuits and Systems, Bydgoszcz, Poland, 22-24 June 2017, 10.23919/MIXDES.2017.8005187.

2-Arefeh Soltani, Roozbeh Abdollahi and Sarang Kazeminia, Programmable incrementing/decrementing binary accumulator for high-speed calibration loops,IEEE International Conference on Electronics، Circuits and Systems (ICECS), Monte Carlo, Monaco, France, 11-14 December 2016, https://ieeexplore.ieee.org/document/7841282.

3-Sarang Kazeminia and Arefeh Soltani, Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switch,IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, South Korea, 25-28 October 2016, https://ieeexplore.ieee.org/document/7803901.

4-Sarang Kazeminia and Arefeh Soltani, Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs,IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, South Korea, 25-28 October 2016, https://ieeexplore.ieee.org/document/7804064.

5-Sarang Kazeminia, Sina Mahdavi, A 800MS/s 150µV input-referred offset single-stage latched comparator,2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, Poland, 23-25 June 2016, https://ieeexplore.ieee.org/document/7529726.

6-Sarang Kazeminia, Sina Mahdavi, Khayrollah Hadidi, Digitally-assisted offset cancellation technique for open loop residue amplifiers in high-resolution and high-speed ADCs,23rd International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2016, Lodz, Poland , June 2016, 10.1109/MIXDES.2016.7529731.

7-Sarang Kazeminia, Sina Mahdavi, Reza Gholamnejad, Bulk controlled offset cancellation mechanism for single-stage latched comparator,23rd International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2016, Lodz, Poland, June 2016, https://ieeexplore.ieee.org/document/7529726.

8-Sarang Kazeminia, Obalit Shino, Dual-loop enhanced-gain fast-response CMFB for open-loop RAs in high-resolution ADCs,24th Iranian Conference on Electrical Engineering (ICEE 2016), Shiraz, Iran, May 2016, https://ieeexplore.ieee.org/document/7585656.

9-Arash Hejazi, Sarang Kazeminia, Roozbeh Abdollahi, A Digitally Assisted 20MHz-600MHz 16-Phase DLL Enhanced with Dynamic Gain Control Loop,22th European Conference on Circuit Theory and Design, Trondheim, Norway, 24-26 Aug 2015, https://ieeexplore.ieee.org/document/7300073.

10-Sarang Kazeminia, Sobhan Sofi Mowloodi, Khayrollah Hadidi, Wide-Range 16-Phases DLL Based on Improved Dead- Zone Phase Detector and Reduced Gain Charge Pump,22nd Iranian Conference on Electrical Engineering, ICEE2014, Tehran, Iran, 20-22 May 2014, https://ieeexplore.ieee.org/document/6999518.

11-Nahid Salehjoo, Sarang Kazeminia, Khayrollah Hadidi, Producing Flat Supply Voltage Using A Temperature-Compensated BGR within LDO Regulator Loop,22nd Iranian Conference on Electrical Engineering, ICEE2014, Tehran, Iran, 20-22 May 2014, https://ieeexplore.ieee.org/document/6999521.

12-Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei, A 10-Bit 50MS/s Pipeline ADC Based on Kickback-Rejected Comparators Improved or Small-Amplitude Inputs,22nd Iranian Conference on Electrical Engineering, ICEE2014, Tehran، Iran, 20-22 May 2014, https://ieeexplore.ieee.org/document/6999570.

13-Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei, On the Stability of Integer-N Phase Locked Loops Based on a Straightforward Design Methodology,22nd Iranian Conference on Electrical Engineering, ICEE2014, Tehran، Iran, 20-22 May 2014, https://ieeexplore.ieee.org/document/6999520.

14-Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei, A 250MHz to 4GHz Adaptive Bias Tuned PLL for Low-Jitter Applications Based on a fast Response VCO Oscillating Cells,22nd Iranian Conference on Electrical Engineering, ICEE2014, Tehran، Iran, 20-22 May 2014, https://ieeexplore.ieee.org/document/6999519.

15-Sarang Kazeminia, Obalit Shino, Ehsan Haghigh, Khayrollah Hadidi, Abdollah Khoei, Improved Single-Stage Kickback-Rejected Comparator for High Speed and Low Noise Flash ADCs,21th European Conference on Circuit Theory and Design, Dresden, Germany, 8-12 Sept. 2013, pp:1-4.

16-Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei, A low jitter 110MHz 16-phase delay locked loop based on a simple and sensitive phase detector,21st Iranian Conference on Electrical Engineering (ICEE), Mashhad, Iran, 14-16 May 2013, https://ieeexplore.ieee.org/document/6599743.

17-Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei, Mohammad-Naghi Azarmanesh, Effect of Bandgap Energy Temperature Dependence on Thermal Coefficient of Bandgap Reference Voltage,2011 20th European Conference on Circuits Theory and Design (ECCTD), Linköping, Sweden, 29-31 August, 2011, 10.1109/ECCTD.2011.6043383.

18-Sarang Kazeminia, Roozbeh Abdollahi, Khayrollah Hadidi, Abdollah Khoei, On Matching Properties of R-2R Ladders in High Performance Digital-to-Analog Converters,18th Iranian Conference on Electrical Engineering (ICEE2010), Isfahan, Iran, 11-13 May, 2010, pp: 432-436.

19-Sarang Kazemi Nia, Yashar Hesamiafshar, Khayrollah Hadidi, Abdollah Khoei, An 8-bit 2.5GS/s D/A converter in 0.35µ CMOS technology with improved pipeline structure,18th Iranian Conference on Electrical Engineering (ICEE2010), Isfahan، Iran, 11-13 May، 2010, pp: 426-431.

20-Sarang Kazeminia, Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei, High-Speed Low-Power Single-Stage Latched-Comparator with Improved Gain and Kickback Noise Rejection,2010 Asia Pacific Conference on Circuits and Systems, Kuala Lumpur، Malaysia, 6-9 December، 2010, 10.1109/APCCAS.2010.5774848.

21-Mohammad Soleimani, Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, Design of High-speed and High-precision Voltage-mode MAX-MIN Circuits with Low Area and Low Power Consumption,European Conference on Circuit Theory and Design (ECCTD)، Antalya، Turkey, 23-27 October، 2009, pp، 351-354.

22-Sarang Kazemi Nia, Khayrollah Hadidi, Abdollah Khoei, An Open Loop Phase Shifter and Frequency Synthesizer,The 14th IEEE International Conference on Electronics Circuits and Systems (ICECS), Marrakech, December 2007, pp، 653-656.

23-Sarang Kazemi Nia, Abdollah Khoei, Khayrollah Hadidi, High Speed High Precision Voltage-Mode MAX and MIN Circuits,The 13th IEEE International Conference on Electronics Circuits and Systems (ICECS), Nice Acropolis، Nice، France, 23-27 Aug. 2009, 10.1109/ECCTD.2009.5274998.

24-Sarang Kazemi Nia, Ghaznavi-Ghoushchi, Extracting IP-Cores of a Digital Design for New Top-Down Binding and Reuse of HDL Modules,15th Conference on Electrical Engineering, Tehran، Iran, ICEE15_195.

25-Rasoul Amirfattahi, Sarang Kazeminia, Majid Mahmoudvand, Automatic Detection of the Matched Gear in Tortion Bar of Peugeot 206،4th Conference on Machine-Vision and Image Processing,Mashhad, Iran, Feb 2006.
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