A Low Power 13Bit 50MS/s Recirculating Pipeline Analog to Digital Converter

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 &mum CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 &mum technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm&ndash0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.