700 MHz–1.4 GHz and 30–70%, Frequency, and Duty-Cycle Locking Loop

Pulse width detection is an important issue, especially in PWM systems. Usually, in data receivers, PLLs are used to recover clock/data frequency or phase, and another circuit is used to reconstruct the pulse width. In this paper, a new locking loop is introduced which can lock to the duty cycle of the input signal, as well as to its phase and frequency. The main advantage is that the three characteristics are detected. The frequency range of the input signal is 700 MHz to 1.4 GHz with the duty cycle range of 30&ndash70%, where the output signal of the suggested loop can be tracked in this range according to various simulation results in different situations. The circuit is designed and simulated using 0.18 um standard CMOS process parameters. The whole loop consumes about 10 mW using a 1.8 v power supply and the output signal RMS-jitter for 2000 cycles after loop locking is 3ps at 1 GHz frequency.