• سارنگ کاظمی نیا

  • دانشیار
  • گروه مهندسی برق
Email:   
WebSite: https://faculty.uut.ac.ir/kazeminia

بیوگرافی کوتاه

          

Sarang Kazeminia was born in 1982, Tonekabon, Iran. He received BS degree in Electrical engineering from Isfahan University of Technology (IUT), Isfahan, Iran, 2004, MS degree in Electrical engineering from Urmia University, Urmia, Iran, 2007, and PhD degree in Electrical Engineering (Analog and Digital IC Design) from Urmia University, Urmia, Iran, 2014. His Ph.D thesis was &ldquoDesign, Layout and Fabrication of 14-bit 500MS/s A/D Converter in 0.18µm CMOS Technology&rdquo. He currently works as an assistant professor in the faculty of Electrical Engineering, Urmia University of Technology, Urmia, Iran.  His research interests are high-speed high-resolution digital-to-analog and analog-to-digital converter design, low-jitter clock generation, phase locked loops, delay locked loops and frequency synthesizer Design. He also have good experiments in the area of digital signal processing and  implementation on FPGA chips
         
    

رزومه آموزشی و پژوهشی

[English CV]

تحصیلات/دوره های دانشگاهی (4)

مقالات ژورنال (20)

مقالات و خلاصه مقالات ارائه شده در همايش ها (25)

اختراع ها و امتیازهای معنوی (3)

جوایز و افتخارات (2)
   
  • نام و نام خانوادگی
  • سارنگ کاظمی نیا
  • مدرک تحصیلی
  • دکترای تخصصی
  • درجه علمی
  • دانشیار
  • بخش مربوطه
  • گروه مهندسی برق
 
        بیوگرافی کوتاه

Sarang Kazeminia was born in 1982, Tonekabon, Iran. He received BS degree in Electrical engineering from Isfahan University of Technology (IUT), Isfahan, Iran, 2004, MS degree in Electrical engineering from Urmia University, Urmia, Iran, 2007, and PhD degree in Electrical Engineering (Analog and Digital IC Design) from Urmia University, Urmia, Iran, 2014. His Ph.D thesis was &ldquoDesign, Layout and Fabrication of 14-bit 500MS/s A/D Converter in 0.18µm CMOS Technology&rdquo. He currently works as an assistant professor in the faculty of Electrical Engineering, Urmia University of Technology, Urmia, Iran.  His research interests are high-speed high-resolution digital-to-analog and analog-to-digital converter design, low-jitter clock generation, phase locked loops, delay locked loops and frequency synthesizer Design. He also have good experiments in the area of digital signal processing and  implementation on FPGA chips

 
 
         
     رزومه آموزشی و پژوهشی

تحصیلات/دوره های دانشگاهی (4)


1-.

2- دکترای تخصصی الکترونیک - مدارهای مجتمع،دانشگاه ارومیه، 1393.

3- کارشناسی ارشد الکترونیک - مدارهای مجتمع،دانشگاه ارومیه، 1386.

4- کارشناسی مهندسی برق-الکترونیک،دانشگاه صنعتی اصفهان، 1383.

مقالات ژورنال (20)


1-Hojjat Aminnejhad, Sarang Kazeminia, and Mortaza Aliasghary, Robust sliding-mode control for maximum power point tracking of photovoltaic power systems with quantized input signal,Optik, 2021, Volume 247, December 2021, 167983.

2-Sarang Kazeminia, Arefeh Soltani, A low-jitter leakage-free digitally calibrated phase locked loop,Computers & Electrical Engineering, 2020, https://www.sciencedirect.com/science/article/abs/pii/S0045790620307187.

3-Sarang Kazeminia, Frequency-range enhanced delay locked loop based on varactor-loaded and current-controlled delay elements,AEU - International Journal of Electronics and Communications, 2020, https://www.sciencedirect.com/science/article/abs/pii/S1434841120315545.

4-S Mahdavi, S Kazeminia, K Hadidi, A 17 MS/s SAR ADC with energy-efficient switching strategy,Analog Integr Circ Sig Process (Springer), 2020, https://link.springer.com/article/10.1007/s10470-020-01634-9.

5-SarangKazeminia، Amir LaalShahsavar، Dual-path linearization technique for bandwidth enhancement in SAH circuits،AEU - International Journal of Electronics and Communications، 2019، https://www.sciencedirect.com/science/article/pii/S1434841119302717.

6-Sarang Kazeminia، Sina Mahdavi، Offset Cancellation in a 800MS/s Single-Stage Comparator by Analog Trimming on the Body Voltage of PMOS Devices،TABRIZ JOURNAL OF ELECTRICAL ENGINEERING، 2019، https://tjee.tabrizu.ac.ir/article_9125.html.

7-Sarang Kazeminia، A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs،Integration، The VLSI Journal، 2019، https://scinapse.io/papers/2900838594.

8-Sarang Kazeminia، Sina Mahdavi، Highly-matched sub-ADC cells for pipeline analogue-to-digital converters،International Journal of Electronics، 2019، https://www.tandfonline.com/doi/abs/10.1080/00207217.2019.1625969?journalCode=tetn20.

9-Sarang Kazeminia، Reza Abdi Behnagh، Milad Kalabkhani، Design and Manufacturing of a Low-Power Dual-Axis Sun Tracker Based on Novel Mechanical and Electrical Detectors. Modares Mechanical Engineering،Modares Mechanical Engineering، 2018، https://mme.modares.ac.ir/article-15-16101-fa.html.

10-Ali Ansari، Reza Abdi Behnagh، Dong Lin، Sarang Kazeminia، Modelling of Friction Stir Extrusion using Artificial Neural Network (ANN)،International Journal of Advanced Design and Manufacturing Technology، 2018، http://www.iaujournals.ir/article_668308.html.

11-Sarang Kazeminia، Roozbeh Abdollahi، Arash Hejazi، A fast-locking low-jitter digitally-enhanced DLL dynamically controlled for loop-gain and stability،Analog Integrated Circuits and Signal Processing، Springer، March 2018، https://link.springer.com/article/10.1007/s10470-018-1109-5.

12-Sarang Kazeminia، Khayrollah Hadidi، A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs،Integration، The VLSI Journal، Elsevier، 2018، https://www.sciencedirect.com/science/article/abs/pii/S0167926017302407.

13-Sarang Kazeminia، Sobhan Sofi Mowloodi، Khayrollah Hadidi، A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump،Journal of Circuits System and Computers، 2015، https://www.semanticscholar.org/paper/A-80-MHz-to-410-MHz-16-Phases-DLL-Based-on-Improved-Kazeminia-Mowloodi/92ec604f8e0063776302f63c1a737ccdd819feda.

14-Sarang Kazeminia، Khayrollah Hadidi، Abdollah Khoei، A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs،Journal of Circuits Systems and Computers، 2015، https://worldscientific.com/doi/10.1142/S0218126615501042.

15-Sarang Kazeminia، Obalit Shino، Ehsan Haghigh، Khayrollah Hadidi، Speed Enhancement and Kickback noise reduction in single-stage latched comparator improved for high-speed and low-noise analogue-to-digital converters،International Journal of Electronics Letters، Taylor & Francis، 2015، https://www.tandfonline.com/doi/abs/10.1080/21681724.2015.1092592.

16-Sarang Kazeminia، Khayrollah Hadidi، Abdollah Khoei، Reanalyzing the basic bandgap reference voltage circuit considering thermal dependence of bandgap energy،Analog Integrated Circuits and Signal Processing، Springer، 2014، https://link.springer.com/article/10.1007/s10470-013-0248-y.

17-Sarang Kazeminia، Khayrollah Hadidi، Abdollah Khoei، A Novel Open Loop Structure for Phase Shifting and Frequency Synthesizing،IEICE Transactions on Fundamentals of Electronics، Communications and Computer Sciences، Volume E91-A Issue 2، Pages 491-496، https://www.jstage.jst.go.jp/article/transfun/E91.A/2/E91.A_2_491/_article.

18-Sarang Kazeminia، Abdollah Khoei، Khayrollah Hadidi، A Low-Jitter 20-110MHz DLL Based on a Simple PD and Common-Mode Voltage Level Corrected Differential Delay Elements،Journal of Information Systems & Telecommunication، 2014، https://www.semanticscholar.org/paper/A-LOW-JITTER-20-110-MHZ-DLL-BASED-ON-A-SIMPLE-PD-Sarang-Khayrollah/8d8d3a4950b4e42c5a5590602efcaa9b6e626631.

19-Sarang Kazeminia، Morteza Mousazadeh، Khayrollah Hadidi، Abdollah Khoei، A 500MS/s 600µW 300µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35µm 3.3v CMOS Process،IEICE Transactions on Electronics، 2011، https://www.semanticscholar.org/paper/A-500-MS%2Fs-600-%C2%B5W-300-%C2%B5m2-Single-Stage-and-Kickback-Kazeminia-Mousazadeh/20832896a51c23e19cccfce8f2d2494fb3c5833e.

20-Sarang Kazeminia، Abdollah Khoei، Khayrollah Hadidi، High Speed High Precision Voltage-Mode MAX and MIN Circuits،Journal of Circuits، Systems and Computers، 2007، https://www.semanticscholar.org/paper/High-Speed-High-Precision-voltage-Mode-Max-and-Min-Kazeminia-Khoei/ee96eefecf9ca84a9e917857c6e045fcae3758d6.

مقالات و خلاصه مقالات ارائه شده در همايش ها (25)


1-Rasoul Amirfattahi، Sarang Kazeminia، Majid Mahmoudvand، Automatic Detection of the Matched Gear in Tortion Bar of Peugeot 206،4th Conference on Machine-Vision and Image Processing، Mashhad، Iran، Feb 2006.

2-Sarang Kazemi Nia، Ghaznavi-Ghoushchi، Extracting IP-Cores of a Digital Design for New Top-Down Binding and Reuse of HDL Modules،15th Conference on Electrical Engineering، Tehran، Iran، 2007.

3-Sarang Kazemi Nia، Abdollah Khoei، Khayrollah Hadidi، High Speed High Precision Voltage-Mode MAX and MIN Circuits،The 13th IEEE International Conference on Electronics Circuits and Systems (ICECS)، 1-4244-0395-2، Nice Acropolis، Nice، France، December 10-13، 2006، pp، 272-275.

4-Sarang Kazemi Nia، Khayrollah Hadidi، Abdollah Khoei، An Open Loop Phase Shifter and Frequency Synthesizer،The 14th IEEE nternational Conference on Electronics Circuits and Systems (ICECS) ، 978-1-4244-1377-5، Marrakech، December 2007، pp، 653-656.

5-Mohammad Soleimani، Abdollah Khoei، Khayrollah Hadidi، Sarang Kazeminia، Design of High-speed and High-precision Voltage-mode MAX-MIN Circuits with Low Area and Low Power Consumption،European Conference on Circuit Theory and Design (ECCTD)، 978-1-4244-3896-9،Antalya، Turkey، 23-27 October، 2009، pp، 351-354.

6-Sarang Kazeminia، Morteza Mousazadeh، Khayrollah Hadidi، Abdollah Khoei، High-Speed Low-Power Single-Stage Latched-Comparator with Improved Gain and Kickback Noise Rejection،2010 Asia Pacific Conference on Circuits and Systems، 978-1-4244-7456-4، Kuala Lumpur، Malaysia، 6-9 December، 2010.

7-Sarang Kazemi Nia، Yashar Hesamiafshar، Khayrollah Hadidi، Abdollah Khoei، An 8-bit 2.5GS/s D/A converter in 0.35µ CMOS technology with improved pipeline structure،18th Iranian Conference on Electrical Engineering (ICEE2010)، 978-1-4244-6760-0، Isfahan، Iran، 11-13 May، 2010، pp، 426-431.

8-Sarang Kazemi Nia، Roozbeh Abdollahi، Khayrollah Hadidi، Abdollah Khoei، On Matching Properties of R-2R Ladders in High Performance Digital-to-Analog Converters،18th Iranian Conference on Electrical Engineering (ICEE2010)، 978-1-4244-6760-0، Isfahan، Iran، 11-13 May، 2010، pp، 432-436.

9-Sarang Kazeminia، Khayrollah Hadidi، Abdollah Khoei، Mohammad-Naghi Azarmanesh، Effect of Bandgap Energy Temperature Dependence on Thermal Coefficient of Bandgap Reference Voltage،2011 20th European Conference on Circuits Theory and Design (ECCTD)، 978-1-4577-0616-5، Linköping، Sweden، 29-31 August، 2011.

10-Sarang Kazeminia، Khayrollah Hadidi، Abdollah Khoei، A low jitter 110MHz 16-phase delay locked loop based on a simple and sensitive phase detector،21st Iranian Conference on Electrical Engineering (ICEE).

11-Sarang Kazeminia، Obalit Shino، Ehsan Haghigh، Khayrollah Hadidi، Abdollah Khoei، Improved Single-Stage Kickback-Rejected Comparator for High Speed and Low Noise Flash ADCs،21th European Conference on Circuit Theory and Design، Dresden، Germany، 8-12 Sept. 2013، pp:1-4.

12-Sarang Kazeminia، Khayrollah Hadidi، Abdollah Khoei، A 250MHz to 4GHz Adaptive Bias Tuned PLL for Low-Jitter Applications Based on a fast Response VCO Oscillating Cells،22nd Iranian Conference on Electrical Engineering، ICEE2014، Tehran، Iran، April2014.

13-Sarang Kazeminia، Khayrollah Hadidi، Abdollah Khoei، On the Stability of Integer-N Phase Locked Loops Based on a Straightforward Design Methodology،22nd Iranian Conference on Electrical Engineering، ICEE2014، Tehran، Iran، April2014.

14-Sarang Kazeminia، Khayrollah Hadidi، Abdollah Khoei، A 10-Bit 50MS/s Pipeline ADC Based on Kickback-Rejected Comparators Improved or Small-Amplitude Inputs،22nd Iranian Conference on Electrical Engineering، ICEE2014، Tehran، Iran، April2014.

15-Nahid Salehjoo، Sarang Kazeminia، Khayrollah Hadidi، Producing Flat Supply Voltage Using A Temperature-Compensated BGR within LDO Regulator Loop،22nd Iranian Conference on Electrical Engineering، ICEE2014، Tehran، Iran، April2014.

16-Sarang Kazeminia، Sobhan Sofi Mowloodi، Khayrollah Hadidi، Wide-Range 16-Phases DLL Based on Improved Dead- Zone Phase Detector and Reduced Gain Charge Pump،22nd Iranian Conference on Electrical Engineering، ICEE2014، Tehran، Iran، April2014.

17-Arash Hejazi، Sarang Kazeminia، Roozbeh Abdollahi، A Digitally Assisted 20MHz-600MHz 16-Phase DLL Enhanced with Dynamic Gain Control Loop،22th European Conference on Circuit Theory and Design، 24-26 Aug 2015، Trondheim، Norway.

18-Sarang Kazeminia and Obalit Shino، Dual-loop enhanced-gain fast-response CMFB for open-loop RAs in high-resolution ADCs،24th Iranian Conference on Electrical Engineering (ICEE 2016)، May 2016، Shiraz، Iran.

19-Sarang Kazeminia، Sina Mahdavi and Khayrollah Hadidi، Digitally-assisted offset cancellation technique for open loop residue amplifiers in high-resolution and high-speed ADCs،23rd International Conference "Mixed Design of Integrated Circuits and Systems"، MIXDES 2016، Lodz، Poland، June 2016.

20-Sarang Kazeminia، Sina Mahdavi and Reza Gholamnejad، Bulk controlled offset cancellation mechanism for single-stage latched comparator،23rd International Conference "Mixed Design of Integrated Circuits and Systems"، MIXDES 2016، Lodz، Poland، June 2016.

21-Sarang Kazeminia and Sina Mahdavi، A 800MS/s، 150µV input-referred offset single-stage latched comparator،MIXDES 2016، Lodz، Poland، June 2016.

22-Sarang Kazeminia and Arefeh Soltani، Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs،IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)، 25-28 October 2016، Jeju، South Korea.

23-Sarang Kazeminia and Arefeh Soltani، Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switch،IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)، 25-28 October 2016، Jeju، South Korea.

24-Arefeh Soltani، Roozbeh Abdollahi and Sarang Kazeminia، Programmable incrementing/decrementing binary accumulator for high-speed calibration loops،IEEE International Conference on Electronics، Circuits and Systems (ICECS)، 11-14 December 2016، Monte Carlo، Monaco، France.

25-Sarang Kazeminia، Maryam Ghafoorzadeh، Faeze Noruzpur، An extendable global clock high-speed binary counter compatible to the FPGA CLBs،24th International Conference on Mixed Design of Integrated Circuits and Systems، 22-24 June 2017، Bydgoszcz، Poland.

اختراع ها و امتیازهای معنوی (3)


1-مهدی خداوردی زاده، سارنگ کاظمی نیا، دستگاه طیف بین مرئی و مادون قرمز فوق سبک پرتابل با استفاده از دوربین دیجیتال به شماره ثبت 92147،اداره ثبت اختراعات، مرکز مالکیت معنوی قوه قضائیه، 1397.

2-سارنگ کاظمی نیا، مهدی خداوردی زاده، کیوان قربانی، پردازشگر مرکزی ربات استتارگر با قابلیت تشخیص بیش از 1024 رنگ و بازسازی رنگها روی صفحه نمایش به شماره ثبت 92780،اداره ثبت اختراعات، پایگاه مالکیت معنوی قوه قضائیه، 1396.

3-سارنگ کاظمی نیا، میلاد کلب خانی، آشکارساز مکانیکی-الکترونیکی برای افزایش کارآیی دنبال کننده های دومحوره خورشیدی به شماره ثبت 97135،پایگاه مالکیت معنوی، اداره ثبت اختراعات، قوه قضائیه ، 1396.

جوایز و افتخارات (2)


1- برگزيده در اولين دوره جشنواره حضرت علی اکبر(ع) به عنوان چهره برتر علمی و دانشگاهی در استان آذربايجان غربی ، 1388.

2- نخبه سطح دو مورد تأیید بنياد ملی نخبگان کشور به عنوان دانش آموخته برتر دوره کارشناسی ارشد و دکترا، 1387.
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